VLSI IMPLEMENTATION OF OPTIMIZED TIME DELAY FOR 32-BIT ALU - SAURABH RAI, SIDDHARTH SAINI, PRAKASH CHANDRA JOSHI, SNEHIL SINGH (Design Engineering, 2021)
In this paper, we provide a 32-bit ALU with an optimized delay time that replaces an existing irreversible logic gate with a reversible logic gate. All processors use the Arithmetic Logic Unit (ALU) for arithmetic and logical functions. It’s also a crucial component in the development of digital systems. ALU (Arithmetic Logic Unit) is an important component of all systems and can be found on various devices such as computers, computers and mobile phones. Peres gates and Fredkin gates were utilized to create 32-bit ALUs that exchange AND, OR with each 1-bit ALU circuit. The design used here can operate faster while using less area than a traditional ALU processor. We investigated the design of ALU and cache memory for use with high-performance CPUs. Looking at the current situation, power consumption, heat dissipation, size and speed are major challenges in the semiconductor industry. Reducing the size of a single computing element can increase speed, and reducing power loss reduces heat loss. Reversible logic has become increasingly important over the last few years due to its potential to reduce power consumption, which is an important requirement for low power design. This method helps reduce power consumption and loss. In this study, we compare the reversible logic-based ALU architecture and the general logic gate-based ALU architecture in terms of power consumption and delay time to improve the performance of the ALU circuit. Xilinx ISE 14.7 is used to synthesize and simulate the effects of the proposed technology.