Auto Reconfigurable RO PUF for FPGA Centric Firmware Authentication and Secure Boot Applications
In today's world, data security is the most national and international concern due to the increase of privacy risks and data breaches. Implementing a secure boot is an effective step in making it happen. It helps in ensuring device boot using only firmware that is trusted by the manufacturer. RISC-V, an open ISA that is best suited for modification and optimization by the user according to the usage requirements. In the mentioned research work, we have proposed a module of secure key generation using the variations of FPGA and a PUF architecture with CRO and RO Vernier TDC for usage in the boot mechanism for RISC-V based processors. The RTL design for the proposed PUF along with other PUFs mentioned in works of literature was studied by modeling in Verilog, synthesized for DigilentNexys A7 FPGA boards using Vivado and for Altera Cyclone IV device. The proposed PUF is characterized and results are tabulated.