Vedic Mathematics: An Approach for Parallel Computing

Abstract

The title discloses the development and statistical analysis of concurrent vedic multiplier architecture;which can be applied in different exercises of parallel computing applications, using modern concurrent hardware architectures. In this research work, the most hardware intensive component that is multiplier architecture is described using principles of vedic mathematics. The architecture of the multiplier is described using fundamentals of Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The development of the architecture is carried out using the recent High Level Synthesis (HLS) Tool like Xilinx Vivado 2018.2. The architecture is targeted to different variants of the FPGA like general purpose, automotive, military purpose or high reliability environment, in order to assure the critical parameters like delay, frequency, resources and power, precisely.