A Low Power Binary Square Rooter using Reversible Logic and Modified Non-Restoring Algorithm

Abstract

The calculation of the square root is a fundamental mathematical operation that has a broad variety of applications. The design of a square rooter must accomplish low power consumption, small footprint, and fast speed. On many occasions, there might be a trade-off between the three measures. Because modern technology strives for low power consumption, designs must undergo significant architectural alteration. An ultra-low-power binary square rooter based on reversible circuitry and a modified non-restoring algorithm is presented in this study. It achieves low power by the use of reversible logic. The binary square rooter is created and implemented using the RCSM programming language (Reversible Controlled Subtract Multiplexer). SRG is used to create a binary square rooter, which allows for additional improvement in areas such as number of quantum costs, garbage outputs, and constant inputs (Samiur Rahman Gate). The binary square rooter is created utilising both the SRG and the traditional approaches, and it uses a non-restoring method. Power is determined by utilising the X-Power Analyzer in conjunction with ModelSim software, which is used to carry out the simulations. The power gained using the SRG approach and the standard technique are both compared.