A High Flexible Low-Latency Memory Based 5G FFT Processor

Abstract

Fourier fast transform (FFT) is a programmable high-throughput processor intended to handle 16- through 4096-point FFT and 12 to 2400-point discrete 4G, wireless local area and future 5G transformers (DFTs).As an agreement between performance and costs, a 16-path data parallel architecture is chosen for the memory. Several enhancements have been made to build a hardware-efficient high-speed CPU. A reconfigurable butterfly unit, comprising eight parallel to radix-2, four parallel to radix-3/4, two parallel to radix-5/8 and one radix-16, is suggested to enable computation for optimum use of hardware resources. Twiddle factor multipliers are improved and compared with various methods. Finally, modified co-ordinate rotation is developed to reduce hardware costs while enabling both FFTs and DFTs. An optimal conflict-free access method for numerous butterflies is also proposed at all roots. The processor may be implemented using a processor synthesizer and designed as an IP (application specific instruction-set processor designer).