Design And Analysis Of Cmos Based Low Power And High Security Data Transmission Using 7t Sram Bit Cell

  • M.ANUSHA,
Keywords: Poweer analysis sram design 6t sram 7t sram power dissipation

Abstract

Memory is an inherent feature of any integrated gadget in today's digital age. It also has a significant role in the overall circuit power. With the increasing worry for portable equipment, nanotechnology grabs chip manufacturers' gaze day after day. However, the power drain is mostly used by static random access in portable devices. As technology increases leak power, the dynamic energy consumption plays a crucial role. Therefore, in our suggested SRAM memory we implemented a power gating mechanism to reduce the energy consumption needed for our day. Another feature was implemented to decrease the leaking power. Since the PMOS and NMOS leakage current is similar in sizes. In addition, the pass semiconductor of SRAM cells are replaced by PMOS to lower the leakage power use instead of using NMOS.

Published
2021-10-14
How to Cite
M.ANUSHA,. (2021). Design And Analysis Of Cmos Based Low Power And High Security Data Transmission Using 7t Sram Bit Cell. Design Engineering, 4232-4242. Retrieved from http://thedesignengineering.com/index.php/DE/article/view/5368
Section
Articles