Fault Tolerant Arithmetic and Logic Unit in Reversible Logic for Low Power Applications

Abstract

To meet expectations of the futuristic technologies, thrust is on fast communication, low power, high computational speeds with delay intolerance. VLSI technology is laboring to meet the demands by incorporating low-power solutions to improve performance. Component size has come to Nano scales however, it has challenges of managing heat dissipation and physical limitations in fabrication. Reversible logic technology has gained momentum in research due to its prominence in Quantum computing and zero power dissipation. The arithmetic and Logic Unit is the significant component of any computing architecture, carrying out operations rigorously while consuming power for the endurance of performance. The proposed approach of designing the fault-tolerant Arithmetic and Logical Unit (ALU) in reversible logic for future computers. Analysis of the proposed design to existing designs is on the quantum cost (QC), garbage output (GO), ancilla input (AI), gate utilization (GC) and number of operations achieved. Improvements observed is at an average of 70% in AI and GC, 59% in QC , 53% in GO and operations are up by 33% to cater to the least power consumption applications.