Low Power Multi Valued Combinational Logic Gates Design using Carbon Nanotubes

  • A. Latha. A, S. Murugeswaran, Dr. G. Yamuna
Keywords: CNTFET, Low Power, Combinational Logics, Multi valued Logic, Ternary Logic, Ternary Half Adder, Ternary Full adder, Ternary Decoder, Power Delay Product (PDP).

Abstract

Thrust for low power circuit design has reached a peak momentum as the MOSFET device scaling touched the lowest possible nanotechnology node. This also leads to complication in designing as the performance and reliability of the circuit are not to be compromised. This work suggested the new material in replacement for MOSFET, the Carbon Nano tube Field Effect Transistors (CNTFET).   Based on the structural and electrical properties they exhibited, these Carbon tubes will be the future building blocks for the new electronics era. In this proposed design, Multi Valued Logics (MVL) especially ternary logic circuits are designed using CNTFET. Ternary Logic gates have an additional state of ‘X’, in addition to ‘0’ and ‘1’. Thus the ‘X’ state considered either ‘0’ or ‘1’ condition which helps to analyze and avoid leakages in the transistors. This helps reduction in power consumption as well. Additionally other combinational logic blocks like Decoders, Half Adders, Full adders with 2 different design concepts were designed using these ternary CNT logic gates.  For Simulation Analysis, the design has been carried out in both CMOS and CNTFET logics using 32nm technology node. The results shows that these CNT ternary logic circuits demonstrate the exceptional performance for propagation delay, Average power and Power Delay Product (PDP) when equated to the regular binary Logic circuits and that of CMOS devices.

Published
2021-09-28
How to Cite
Dr. G. Yamuna, A. L. A. S. M. (2021). Low Power Multi Valued Combinational Logic Gates Design using Carbon Nanotubes . Design Engineering, 14840-14852. Retrieved from http://thedesignengineering.com/index.php/DE/article/view/4771
Section
Articles