Novel Architecture For 16*16 Binary Multiplications Using Redundant Technique

Abstract

The aim of the paper is to implement 16*16 bit binary multiplication using optimized architecture. The proposed architecture reduces the product term and use of parallel architecture concepts leads to improve performance and reduces time complexity. Hardware implementation done through reversible gate on DE2 Altera board and verified the hardware using test benches. Time complexity of the calculation is Equal expansion of two n-digits repetitive parallel numbers can be acted in a consistent time, free of n without convey spread, n bit augmentation is acted in a period relative toPerformance percentage improvement is 21.66%.