Design and Simulation of Area Efficient Carry Select Adder using Verilog HDL

Abstract

In this paper, an Area efficient Carry Select Adder (CSLA) design is Proposed. The Conventional design of carry select adder is faster in comparison with ripple carry adder (RCA) however Conventional CSLA requires larger area. The increased area in conventional CSLA is due to replication of ripple carry adders and presence of multiplexers. In this paper, the analysis is made on the logic operations that are involved in Conventional CSLA and Published CSLA (Base Paper’s CSLA) to identify redundant logic operations. Gate level reduction approach is made, to remove redundant logic operations and to reduce the total area required for the proposed design. In Published CSLA the logic operations are represented in 4 units i) Half Sum Generation unit (HSG) ii) Carry Generation unit (CG) iii) Carry Select unit (CS) iv)Final Sum Generation unit (FSG). In Proposed design, the CG and CS units are combined by removing a number of redundant logic gates and thereby gate count is reduced and hence area reduced. Proposed CSLA when compared with Conventional CSLA there is 25.6% reduction in area and when compared with Published CSLA the area reduced is 6%. The results of Proposed design proves that the design is efficient in terms of Area. The design is simulated and synthesized in Xilinx ISE 14.7 software using Verilog HDL.