PERFORMANCE INVESTIGATION ON CASCADED MULTILEVEL INVERTER FOR AC DRIVE APPLICATION

  • S. Usha, S.Vidyasagar, V. Kalyanasundaram, R. Ramya, T.M. Thamizh Thentral, A. Geetha, R. Palanisamy
Keywords: Cascaded H-bridge inverter, Total harmonics distortion, 13 level output voltage, SPWM, Reduced switch topology

Abstract

This paper proposed a detailed performance investigation of modified reduced switch cascaded multilevel inverter which is depends on cascaded half-bridge that produces a high-power quality, 13-Level Output. The cascaded-multilevel inverter due to its great efficiency in high voltage and power even in low harmonics applications has got the attention in the past few years. A proposed topology with standard specifications needs a total of ‘n’direct current sources to have ‘2n+1’ level output at the end, where n is the inverter stages number. The proposed work is to create a elevated level-inverter output with less number of switches. The MOSFETs are triggered using the fundamental frequency switching method for output voltage level control. At its output, the level generation circuit only produces positive levels. The 13 levels of output produce a nearly sinusoidal waveform for voltage at output, which in turn produces, without the use of filters, build a almost sinusoidal waveform with reduced switches, less harmonics and reduced common mode voltage During both steady and intermittent states, the implemented control strategy performs optimally compared to conventional methods.

Published
2021-08-05
How to Cite
A. Geetha, R. Palanisamy, S. U. S. V. K. R. R. T. T. T. (2021). PERFORMANCE INVESTIGATION ON CASCADED MULTILEVEL INVERTER FOR AC DRIVE APPLICATION . Design Engineering, 6730-6739. Retrieved from http://thedesignengineering.com/index.php/DE/article/view/3173
Section
Articles