PARAMETRIC OPTIMIZATION ON PIPELINED ADC USING TRANSMISSION GATE IN CMOS DESIGN

Abstract

This work is base on the pipeline ADCs architecture. Pipeline ADCs are convenient alternatives to time interleaving the static performance is described by measures of differential and integral nonlinearities. The proposed pipeline ADC consists of two or more stages. In every stage a low-resolution ADC combining these stages results in a higher resolution with reduce power and a optimize area. Each block various schematic and layout models are design and verified through simulation. In this work our use of transmission gate avoids the parasitic capacitances. Due to the use of transmission gate the number of transistors will reduce in design. . The sample ADC design in a 50-nanometer CMOS technology with 8-bit of resolution. The supply voltage is 1.2V.