DESIGN OF LOW POWER MASTER SLAVE D FLIP-FLOP CIRCUIT BY USING ADIABATIC LOGIC

Abstract

Different adiabatic logic circuits could be used to reduce dissipation of electricity. In comparison to CMOS' logic circuit design, two adiabatic logic families, Positive feedback adiabatic logic and Efficient charge recovery logic, were used to improve the circuit operations and effectiveness. A flipflop from MASTER-SLAVE D is proposed in this article to use the simulation of the tanner EDA in 18 Nm technology archives. The simulation results show that Positive feedback adiabatic logic saves more money than Efficient charge recovery logic. We also presented adiabatic flip flops that are used for optical clocking. A competitive and exciting method for reducing dissipations on power in ultralow power digital systems has already emerged as the clocking system utilizing an energy recovery technology. Adiabatic flops are the core elements for adiabatic clocking systems of this kind. The flip flops function in adiabatic terms. This thesis analyses the efficiency of two specific forms of energy recovery flips. This simulation was carried out. Both are single ended conditional flip-flop capture and differential flip capture. The two flip flops use energy recycling schemes. We used a clock gating system along with an energy recovery strategy for improved comparative performance. The simulations are obtained using Tanner EDA 18 nm technology.