DESIGN AND IMPLEMENTATION OF LOW POWER AND HIGH SECURITY DATA INFORMATION USING 7T SRAM BIT CELL

Abstract

In today's digital era, memory is an inevitable part of any integrated device. Also it has a major part in the total circuit power. As the growing concern for portable devices is increasing day by day, the nano-technology is grabbing the eyes of the chip makers. But the drain of power in portable devices which mainly contains static random access memory. As technology scales down Leakage power places important role compared to dynamic power consumption. Hence we used Power gating technique in our Proposed SRAM memory to lower the power consumption which is the need of the day. Also we added another Feature to reduce the leakage power.Since the leakage  current of both PMOS and NMOS with a similar component size. To additionally reduce the leakage  power utilization, rather than utilizing NMOS, the pass semiconductors of SRAM cells are replace by PMOS.