PERFORMANCE EXPLORATION OF AMBA AXI4 STREAM BUS PROTOCOL FOR WIRELESS SENSOR NETWORKS

Abstract

The design phase of the system-on-chip (SoC) meets different coordination problems between the two module. The interconnection of Bus thus plays a major role in the success of the device on a single chip. The standard bus links cease to satisfy the demands of future generation SoC. This document offers an optimised specification of the AXI-4 protocol for the high-speed transmission of data in the SoC application. The proposed interface protocol AXI-4 Stream consists of the master and slave modules and used as a standard interface to connect components that wish to exchange data. The master and slave module finance activities all burst-based transactions. The protocol can also be used while connecting larger numbers of masters and slaves components. The findings from the simulation of the interface AXI-4 stream and its FPGA realisation on Artix-7 show a lower use of resources and a performance benchmark tests between AXI-4 with standard AHB and Wishbone bus components shows the average region minimization and frequency increases respectively of 40 and 41% and also supports wide variety of different stream types.