DESIGN AND IMPLEMENTATION OF SPECULATIVE ADDER FOR HIGH SPEED VLSI ARCHITECTURE
In this paper we outline about the design of Carry Look-ahead Adder (CLA) with the help of inexact speculative adder (ISA). ISA is pipelined with some logic gates so that we can increase the frequency of operation. Consequently, a different stage of scheduled ISA has been clock gated, so that we can reduce the consumed power of the model. Hardware implementation and punctuality verification is done using Field Programmable Gate Array (FPGA) framework. The clock frequency (324MHz) is used for the carry look-ahead adder operation. Power and area analysis of 32 bit scheduled ISA is executed by using CMOS technology. Our design utilized mm2 of chip area with power consumption of 9.68mW which is lesser than conventional speculative adder.