Design of an Efficient Traffic Balance and Fault Tolerant Routing Algorithm for Network on Chip

Abstract

When developing a Network-on-Chip (NoC) architecture, designers must take into account a variety of factors, including bandwidth, performance, energy consumption, cost, reusability, and fault tolerance. It is very difficult to achieve all of these interdependent constraints and goals simultaneously in the majority of design endeavors. Due to their reusability and fault-tolerance characteristics, several of these characteristics may be optimized and satisfied simply by conventional NoC topologies. On the other hand, with irregular NoC topologies, other characteristics like energy consumption, performance, and chip area may be optimized more effectively. In this paper, we offer a routing strategy that is capable of coping with numerous connection failures. These parameters are used to address routing route faults. Experiments demonstrate that the suggested routing methodology is capable of routing packets even when there are two problem sites, and that the packets are received without error at the destination router. This article discusses an effective approach to testing NoC switches online. This solution addresses control failures in NoC switches, i.e. routing errors that result in NoC packets being transmitted to output ports they were not intended for. This work proposes a high-level fault model for switch routing issues. The suggested technique is validated by fault simulation using our high-level fault model. The thorough simulation results demonstrate that the suggested strategy outperforms previous work on a variety of multimedia benchmarks.