FPGA Implementation of High Speed Distributed Arithmetic Optimum Memory Utilized DTCWT Architecture for Image Processing
This paper describes High speed Dual Tree Complex Wavelet (DTCWT) sub band computation is based on multiplexed Distributive Arithmetic Algorithm (DAA). The nominated architecture is memory efficient and operates at frequencies greater than 300 MHz in decomposing. The architectures such as reduced order structure; multiplexed DA structure and high speed DA (HSDA) are designed and evaluated for DTCWT computation performance minimizing arithmetic operations with better latency. The proposed design is modeled in Verilog HDL and is implemented Virtex-5 FPGA considering Xilinx ISE FPGA design flow. The HSDA architecture consumes less than 11% power compared with existing methods for DTCWT implementation. The operating frequency of processing on Virtex-5 platform is 9% faster with less than 12% of FPGA resources occupied.