32 bit Power, Area and delay efficient carry Select Adder Using modified 10T Full Adder

Abstract

In VLSI design With the development in the technology, adder circuits and other all applications are concentrating on high speed and low power requirements. In many data processing CSLA is mainly used It is a faster adder. There is a scope for decreasing the power, area & increase in speed. In this paper, we proposed a system which is designed with CMOS modified 10T full adder. Here less number of transistors are utilized to design full adder. Cadence virtuoso tool is used in 90nm technology. This modified circuit works on pass transistor technology. 90nm technology with supply voltage 1.8V is used. It is designed using 2 inverters and pass transistors. We get full swing voltage at the output. So there is no degraded output for more number of inputs. In this newly designed full adder compare to existing 4T XNOR logic less number of transistors are used so area utilization and power is reduce.