Runtime Redundancy Reconfigurable Fault-Tolerant Static Random Access Memory

Abstract

Fault diagnosis and repair in cache memory has continuously been the thrust area of the research. With the growing technology, the transistor geometrical sizing has reduced drastically. In the emerging sub-threshold nanometer regime, process parameter variations are radically increased. This has resulted in the formation of faults in the memory. As process variations or PVT variations are high, more number of cells might be faulty in the memory. In this paper, the effect of process variation on fault generation in memory is analyzed.  For the smooth maneuver of the circuits, applications, or devices, memory used should be fault-tolerant. A runtime programmable reconfiguration technique is proposed using redundant elements to increase the yield and reliability of memory on system-on-chip. In the proposed reconfiguration technique, a comparison of address with faulty address on each access is reduced to 1-bit to reduce the delay given for each access duration of memory. With the proposed method the reduction in comparison time between the addresses at each access time is reduced by 87.5% for an 8-bit memory address. The power increase given by the proposed method is 0.0353% which is negligible compared to other methods.