Simulation of Optimized Architecture for the Estimation of Congession during Placement and Routing

Abstract

This work presents backend estimation of design parameters for placement and routing flow with the help of existed Floorplan approach done by using Hybrid Optimization Algorithm to estimate the value of Congestion. Effective area utilization plays key role in VLSI Circuit design, wherein reduction of Congestion is also associated with it for the improvement of Floorplan, Placement and Routing. This improvement significantly helpful for compact design and performance of the circuit. Congestion is a fundamental key issue in Very Large Integration for estimating the density of area underlies with routing among various Computational blocks. Here we used ICC II simulation tool for simulation of Floorplanned area of Standard Benchmark Circuit for the betterment of placement. Prior approaches estimated the values of congestion for standard architectures whereas this work considered the Floorplan and Placement outputs of standard MCNCBM Circuit using IHS Algorithm which gave best results for placement and routing for VLSI circuits, and simulated it for the estimation of Congestion for the circuit design